SH7052 Datasheet, PDF (868/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

AUDCK
(input)
t_RMDD
t_RMCYC
t_RMCKW
t_RMDHD
AUDATA3 to 0
(output)
AUDATA3 to 0
(input)
AUDSYNC
(input)
t_RMDS
t_RMDH
t_RMSS
t_RMSH
Figure 24.22 RAM Monitor Mode Timing
24.3.12 UBC Trigger Timing
Table 24.17 shows UBC trigger timing.
Table 24.17 UBC Trigger Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 85°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing flash EEPROM, T_a = –40°C to 85°C.
Item
UBCTRG delay time
Symbol
t _UBCTGD
Min
—
Max
Unit
Figures
35
ns
Figure 24.23
CK
UBCTRG
V_OH
t_UBCTGD
Figure 24.23 UBC Trigger Timing
842