SH7052 Datasheet, PDF (415/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Contention between TCNT Write and Counter Clearing by Overflow: With channel 0 to 5
and 11 free-running counters (TCNT0, TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3 to
TCNT5, TCNT11), if overflow occurs in the T2 state of a CPU write cycle, the write to TCNT has
priority and TCNT is not cleared.
Writing of 1 to the interrupt status flag (OVF) due to the overflow is performed in the same way as
for normal overflow.
The timing in this case is shown in figure 10.66. In this example, H'5555 is written at the point at
which TCNT overflows.
T1
T2
Pø
TCNT input clock
Address
TCNT address
Internal write signal
Overflow signal
TCNT
FFFF
5555
(CPU write value)
5556
Interrupt status flag
(OVF)
Figure 10.66 Contention between TCNT Write and Overflow
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