SH7052 Datasheet, PDF (689/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.2.2 Port A Data Register (PADR)
Bit: 15
14
13
12
11
10
9
8
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DR
DR
DR
DR
DR
DR
DR
DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits
PA15DR to PA0DR correspond to pins PA15/RxD0 to PA0/TI0A.
When a pin functions as a general output, if a value is written to PADR, that value is output
directly from the pin, and if PADR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PADR is read the pin state, not the register value, is
returned directly. If a value is written to PADR, although that value is written into PADR it does
not affect the pin state. Table 19.2 summarizes port A data register read/write operations.
PADR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Table 19.2 Port A Data Register (PADR) Read/Write Operations
Bits 15 to 0:
PAIOR
Pin Function
0
General input
Other than
general input
1
General output
Other than
general output
Read
Pin state
Pin state
PADR value
PADR value
Write
Value is written to PADR, but does not affect pin
state
Value is written to PADR, but does not affect pin
state
Write value is output from pin
Value is written to PADR, but does not affect pin
state
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