SH7052 Datasheet, PDF (815/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

22.2 Operation
The on-chip RAM is controlled by means of the system control register (SYSCR).
When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses to addresses
H'FFFF8000 to H'FFFFAFFF is SH7052F, or accesses to address H'FFFF8000 to H'FFFFBFFF in
SH7053F and SH7054F are then directed to the on-chip RAM.
When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will
return an undefined value, and a write is invalid. If a transition is made to hardware standby mode
after the RAME bit in SYSCR is cleared to 0, the contents of the on-chip RAM are held.
For details of SYSCR, see 23.2.2, System Control Register (SYSCR), in section 23, Power-Down
State.
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