SH7052 Datasheet, PDF (275/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 2—Input Capture/Compare-Match Flag 3C (IMF3C): Status flag that indicates GR3C input
capture or compare-match. The flag is not set in PWM mode.
Bit 2: IMF3C
0
1
Description
[Clearing condition]
(Initial value)
When IMF3C is read while set to 1, then 0 is written to IMF3C
[Setting conditions]
• When the TCNT3 value is transferred to GR3C by an input capture signal
while GR3C is functioning as an input capture register. However, IMF3C
is not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3C while GR3C is functioning as an output compare
register
• Bit 1—Input Capture/Compare-Match Flag 3B (IMF3B): Status flag that indicates GR3B input
capture or compare-match. The flag is not set in PWM mode.
Bit 1: IMF3B
0
1
Description
[Clearing condition]
(Initial value)
When IMF3B is read while set to 1, then 0 is written to IMF3B
[Setting conditions]
• When the TCNT3 value is transferred to GR3B by an input capture signal
while GR3B is functioning as an input capture register. However, IMF3B is
not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3B while GR3B is functioning as an output compare
register
• Bit 0—Input Capture/Compare-Match Flag 3A (IMF3A): Status flag that indicates GR3A
input capture or compare-match. The flag is not set in PWM mode.
Bit 0: IMF3A
0
1
Description
[Clearing condition]
(Initial value)
When IMF3A is read while set to 1, then 0 is written to IMF3A
[Setting conditions]
• When the TCNT3 value is transferred to GR3A by an input capture signal
while GR3A is functioning as an input capture register. However, IMF3A is
not set by input capture with a channel 9 compare match as the trigger
• When TCNT3 = GR3A while GR3A is functioning as an output compare
register
249