SH7052 Datasheet, PDF (387/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

IMF (ICF) Setting Timing in Compare-Match: The IMF bit and CMF bit are set to 1 in the
timer status register (TSR) by the compare-match signal generated when the general register (GR)
output compare register (OCR), or cycle register (CYLR) value matches the timer counter (TCNT)
value. The compare-match signal is generated in the last state of the match (when the matched
TCNT count value is updated).
The timing in this case is shown in figure 10.38.
CK
TCNT input clock
TCNT
N
N+1
GR(CYLR)
N
Compare-match signal
Interrupt status flag
IMF (CMF)
Interrupt request signal
IMI (CMI)
Figure 10.38 IMF (CMF) Setting Timing in Compare-Match
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