SH7052 Datasheet, PDF (7/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Main Revisions and Additions in this Edition
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8
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Item
Revisions (See Manual for Details)
1.3.1 Pin Arrangement
Name of 155 th pin amended (PK11/TO8L)
5.1.1 Types of Exception
Processing and Priority
Table 5.1 Types of Exception Processing and Priority
Order
Compare match timer (CMT1), A/D converter channel 1
(A/D1) added
Module abbreviations amended: CMT0, A/D0
9.3.5 Dual Address Mode
Figure 9.5 Dual Address Mode and Indirect Address
Operation (16-Bit-Width External Memory Space)
Description of 1st and 2nd bus cycles amended
If the data bus is 16 bits wide when the external
memory space is accessed, two bus cycles are
necessary.
10.2.3 Timer Control Registers Timer Control Register 9A, 9B, 9C (TCR9A, TCR9B,
(TCR)
TCR9C) Description of Bits 1 and 0 amended
x=A, C, or E
10.2.15 Free-Running Counters Description of Free-Running Counter 0 added
(TCNT)
When the bits corresponding to the timer start register 1
(TSTR1) are set to 1, this counter starts to count.
Description of Free-Running Counters 1A, 1B, 2A, 2B,
3, 4, 5, 11 added
When the bits corresponding to the timer start register
1, 3 (TSTR1, TSTR3) are set to 1, these counters start
to count.
10.3.1 Overview
Description of Channel 2 amended
Description of Channel 10 amended
10.3.9 PWM Timer Function
Description amended
..., and H'0002, H'0003, H'0004 (100%), and H'0000
(0%) in BFR6A.
10.6 Sample Setup Procedures Sample Setup Procedure for Channel 0 Input Capture
Triggered by Channel 10 Compare-Match
Register name amended
Writing to ROM Area
Description added
Immediately after ATU Register
Write