SH7052 Datasheet, PDF (245/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

10.2.4 Timer I/O Control Registers (TIOR)
The timer I/O control registers (TIOR) are 8-bit registers. The ATU-II has 16 TIOR registers: one
for channel 0, four each for channels 1 and 2, two each for channels 3 to 5, and one for channel 11.
For details of channel 10, see section 10.2.26, Channel 10 Registers.
Channel
0
1
2
3
4
5
11
Abbreviation
Function
TIOR0
ICR0 edge detection setting
TIOR1A to 1D
TIOR2A to 2D
GR input capture/compare-match switching, edge detection/
output value setting
TIOR3A, TIOR3B
TIOR4A, TIOR4B
TIOR5A, TIOR5B
GR input capture/compare-match switching, edge detection/
output value setting, TCNT3 to TCNT5 clear enable/disable
setting
TIOR11
GR input capture/compare-match switching, edge
detection/output value setting
Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input
capture registers and general registers.
For dedicated input capture registers (ICR), TIOR performs edge detection setting.
For general registers (GR), TIOR selects use as an input capture register or output compare
register, and performs edge detection setting. For channels 3 to 5, TIOR also selects enabling or
disabling of free-running counter (TCNT) clearing in the event of a compare-match.
Timer I/O Control Register 0 (TIOR0)
Bit:
Initial value:
R/W:
7
IO0D1
0
R/W
6
IO0D0
0
R/W
5
IO0C1
0
R/W
4
IO0C0
0
R/W
3
IO0B1
0
R/W
2
IO0B0
0
R/W
1
IO0A1
0
R/W
0
IO0A0
0
R/W
TIOR0 specifies edge detection for input capture registers ICR0A to ICR0D.
TIOR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
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