SH7052 Datasheet, PDF (580/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.3.6 HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 15.12 shows a flowchart of the HCAN halt mode.
MCR1 = 1
GSR2 = 1?
(Wait until transmission is
No
completed if in progress)
Bus idle?
Yes
MBCR setting
MCR1 = 0
CAN bus communication possible
: Settings by user
: Processing by hardware
Figure 15.12 HCAN Halt Mode Flowchart
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
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