SH7052 Datasheet, PDF (172/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bits 31 to 29, 27 to 25, 23 to 21, 15, 14, 11, 10, 7, 6—Reserved: These bits are always read as
0, and should only be written with 0.
• Bit 28—Direct/Indirect Select (DI): Specifies either direct address mode operation or indirect
address mode operation for the channel 3 source address. This bit is valid only in CHCR3. It
always reads 0 in CHCR0 to CHCR2, and should always be written with 0.
Bit 28: DI
0
1
Description
Direct access mode operation for channel 3
Indirect access mode operation for channel 3
(Initial value)
• Bit 24—Source Address Reload (RO): Selects whether to reload the source address initial
value during channel 2 transfer. This bit is valid only for channel 2. It always reads 0 in
CHCR0, CHCR1, and CHCR3, and should always be written with 0.
Bit 24: RO
0
1
Description
Does not reload source address
Reloads source address
(Initial value)
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