SH7052 Datasheet, PDF (859/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

24.3.6 I/O Port Timing
Table 24.11 shows I/O port timing.
Table 24.11 I/O Port Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V, PV_CC2 = 5.0 V ± 0.5 V,
AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC, V_SS = PLLV_SS = AV_SS = 0 V,
T_a = –40°C to 85°C.
When writing or erasing flash EEPROM, T_a = –40°C to 85°C.
Item
Port output data delay time
Port input hold time
Port input setup time
Symbol
t _PWD
t _PRH
t _PRS
Min
—
24*¹
24+tcyc
24*¹
24+tcyc
Max
100
—
—
Unit Figures
ns
Figure 24.13
ns
ns
[Operating precautions]
The operation guaranteed voltage range of power supply PV_CC1 in MCU single-chip mode is 5.0 V
±0.5 V. Do not use a voltage outside this range.
*1 The port input signals are asynchronous, but judged to have been changed at CK clock rise
with two-state intervals shown in figure 24.13. If the setup times shown here are not provided,
recognition is delayed until the clock rise two states after that timing.
CK
Port
(read)
Port
(write)
t_PRS t_PRH
t_PWD
Figure 24.13 I/O Port Input/Output timing
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