SH7052 Datasheet, PDF (87/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 5 Exception Processing
5.1 Overview
5.1.1 Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority shown in table 5.1. When several exception processing sources occur at once,
they are processed according to the priority shown.
Table 5.1 Types of Exception Processing and Priority Order
Exception
Reset
Address
error
Interrupt
Source
Power-on reset
Manual reset
CPU address error
DMAC address error
NMI
User break
IRQ
On-chip peripheral modules:
Priority
High
• Direct memory access controller (DMAC)
• Advanced timer unit-II (ATU-II)
• Compare match timer 0 (CMT0)
• A/D converter channel 0 (A/D0)
• Compare match timer (CMT1)
• A/D converter channel 1 (A/D1)
• Serial communication interface (SCI)
• Hitachi controller area network (HCAN)
• Watchdog timer (WDT)
Instructions Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay branch Low
instruction*¹ or instructions that rewrite the PC*²)
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF.
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