SH7052 Datasheet, PDF (232/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Timer Start Register 2 (TSTR2)
Bit:
Initial value:
R/W:
7
STR7D
0
R/W
6
5
STR7C STR7B
0
0
R/W R/W
4
STR7A
0
R/W
3
STR6D
0
R/W
2
STR6C
0
R/W
1
STR6B
0
R/W
0
STR6A
0
R/W
TSTR2 is an 8-bit readable/writable register that starts and stops the free-running counter (TCNT)
in channels 6 and 7.
TSTR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—Counter Start 7D (STR7D): Starts and stops free-running counter 7D (TCNT7D).
Bit 7: STR7D
0
1
Description
TCNT7D is halted
TCNT7D counts
(Initial value)
• Bit 6—Counter Start 7C (STR7C): Starts and stops free-running counter 7C (TCNT7C).
Bit 6: STR7C
0
1
Description
TCNT7C is halted
TCNT7C counts
(Initial value)
• Bit 5—Counter Start 7B (STR7B): Starts and stops free-running counter 7B (TCNT7B).
Bit 5: STR7B
0
1
Description
TCNT7B is halted
TCNT7B counts
(Initial value)
• Bit 4—Counter Start 7A (STR7A): Starts and stops free-running counter 7A (TCNT7A).
Bit 4: STR7A
0
1
Description
TCNT7A is halted
TCNT7A counts
(Initial value)
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