SH7052 Datasheet, PDF (826/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

23.4.2 Canceling Software Standby Mode
Software standby mode is canceled by an NMI interrupt or a power-on reset.
Cancellation by NMI: Clock oscillation starts when a rising edge or falling edge (selected by the
NMI edge select bit (NMIE) in the interrupt control register (ICR) of the INTC) is detected in the
NMI signal. This clock is supplied only to the watchdog timer (WDT). A WDT overflow occurs if
the time established by the clock select bits (CKS2 to CKS0) in TCSR of the WDT elapses before
transition to software standby mode. The occurrence of this overflow is used to indicate that the
clock has stabilized, so the clock is supplied to the entire chip, software standby mode is canceled,
and NMI exception processing begins.
When canceling standby mode with an NMI interrupt, set the CKS2 to CKS0 bits so that the WDT
overflow period is longer than the oscillation stabilization time.
When canceling standby mode with an NMI pin set for falling edge, be sure that the NMI pin level
upon entering software standby (when the clock is halted) is high, and that the NMI pin level upon
returning from software standby (when the clock starts after oscillation stabilization) is low. When
canceling software standby mode with an NMI pin set for rising edge, be sure that the NMI pin
level upon entering software standby (when the clock is halted) is low, and that the NMI pin level
upon returning from software standby (when the clock starts after oscillation stabilization) is high.
Cancellation by Power-On Reset: A power-on reset of the SH7052F/SH7053F/SH7054F caused
by driving the RES pin low cancels software standby mode.
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