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SH7052 Datasheet, PDF (242/919 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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Timer Control Registers 9A, 9B, 9C (TCR9A, TCR9B, TCR9C)
TCR9A
Bit:
Initial value:
R/W:
7
6
5
4
â TRG3BEN EGSELB1 EGSELB0
0
0
0
0
R
R/W
R/W
R/W
3
2
1
0
â TRG3AEN EGSELA1 EGSELA0
0
0
0
0
R
R/W
R/W
R/W
TCR9B
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
â TRG3DEN EGSELD1 EGSELD0 â TRG3CEN EGSELC1 EGSELC0
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R
R/W
R/W
R/W
TCR9C
Bit:
7
â
Initial value:
0
R/W: R
6
5
4
3
â
EGSELF1 EGSELF0
â
0
0
0
0
R
R/W
R/W
R
2
1
0
â EGSELE1 EGSELE0
0
0
0
R
R/W
R/W
⢠Bit 7âReserved: This bit always reads 0. The write value should always be 0.
⢠Bit 6âTrigger Channel 3BEN, 3DEN (TRG3BEN, TRG3DEN): These bits select the channel
9 event counter compare-match signal channel 3 input capture trigger.
Bit 6: TRG3xEN
0
1
x = B or D
Description
Channel 3 input capture trigger in event of channel 9 compare-match
(ECNT9x = GR9x) is disabled
(Initial value)
Channel 3 input capture trigger in event of channel 9 compare-match
(ECNT9x = GR9x) is enabled
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