SH7052 Datasheet, PDF (804/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

A18 to A0
CE
Memory read mode
Address stable
Other mode command write
t_nxtc
t_ces
t_ceh
OE
WE
I/O7 to I/O0
t_wep
t_f
t_r
t_ds
t_dh
Note: Do not enable WE and OE at the same time.
Figure 21.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Table 21.17 AC Characteristics in Memory Read Mode (Conditions: V_CC = 3.3 V ±0.3 V,
V_SS = 0 V, T_a = 25°C ±5°C)
Item
Symbol
Min
Access time
t _acc
CE output delay time
t _ce
OE output delay time
t _oe
Output disable delay time
t _df
Data output hold time
t _oh
5
Max
Unit
Notes
20
µs
150
ns
150
ns
100
ns
ns
A18 to A0
Address stable
Address stable
CE V_IL
OE V_IL
WE V_IH
t_acc
I/O7 to I/O0
t_acc
t_oh
t_oh
Figure 21.23 CE and OE Enable State Read Timing Waveforms
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