SH7052 Datasheet, PDF (243/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bits 5 and 4—Edge Select B1, B0, D1, D0, F1, F0 (EGSELB1, EGSELB0, EGSELD1,
EGSELD0, EGSELF1, EGSELF0): These bits select the event counter counted edge(s).
Bit 5: EGSELx1
0
1
x = B, D, or F
Bit 4: EGSELx0
0
1
0
1
Description
Count disabled
Rising edges counted
Falling edges counted
Both rising and falling edges counted
(Initial value)
• Bit 3—Reserved: This bit always reads 0. The write value should always be 0.
• Bit 2—Trigger Channel 3AEN, 3CEN (TRG3AEN, TRG3CEN): These bits select the channel
9 event counter compare-match signal channel 3 input capture trigger.
Bit 2: TRG3xEN
0
1
x = A or C
Description
Channel 3 input capture trigger in event of channel 9 compare-match
(ECNT9x = GR9x) is disabled
(Initial value)
Channel 3 input capture trigger in event of channel 9 compare-match
(ECNT9x = GR9x) is enabled
• Bits 1 and 0—Edge Select A1, A0, C1, C0, E1, E0 (EGSELA1, EGSELA0, EGSELC1,
EGSELC0, EGSELE1, EGSELE0): These bits select the event counter counted edge(s).
Bit 1: EGSELx1
0
1
x = A, C, or E
Bit 0: EGSELx0
0
1
0
1
Description
Count disabled
Rising edges counted
Falling edges counted
Both rising and falling edges counted
(Initial value)
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