SH7052 Datasheet, PDF (30/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 1.1 SH7052F/SH7053F/SH7054F Features (cont)
Item
Direct memory
access controller
(DMAC)
(4 channels)
Advanced timer
unit-II (ATU-II)
Advanced pulse
controller (APC)
Watchdog timer
(WDT)
(1 channel)
Compare-match
timer (CMT)
(2 channels)
Features
• DMA transfer possible for the following devices:
 External memory, on-chip memory, on-chip peripheral modules
(excluding DMAC, UBC, BSC)
• DMA transfer requests by on-chip modules
 SCI, A/D converter, ATU-II, HCAN
• Cycle steal or burst mode transfer
• Dual address mode
 Direct transfer mode
 Indirect transfer mode (channel 3 only)
• Address reload function (channel 2 only)
• Transfer data width: Byte/word/longword
• Maximum 63 inputs or outputs can be processed
 Four 32-bit input capture inputs
 Twenty-eight 16-bit input capture inputs/output compare outputs
 Sixteen 16-bit one-shot pulse outputs
 Eight 16-bit PWM outputs
 Six 8-bit event counters
 One gap detection function
• I/O pin output inversion function
• Maximum eight pulse outputs on reception of ATU-II (channel 11) compare-
match signal
• Can be switched between watchdog timer and interval timer function
• Internal reset, external signal, or interrupt generated by counter overflow
• Two kinds of internal reset
 Power-on reset
 Manual reset
• Selection of 4 counter input clocks
• A compare-match interrupt can be requested independently for each
channel
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