SH7052 Datasheet, PDF (459/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

13.2.4 Compare Match Timer Constant Register (CMCOR)
The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for
compare match with CMCNT.
CMCOR is initialized to H'FFFF by a power-on reset and in the standby modes. It is not initialized
by a manual reset.
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
13.3 Operation
13.3.1 Cyclic Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 13.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Figure 13.2 Counter Operation
Time
433