SH7052 Datasheet, PDF (187/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

External memory space → External memory space
(External memory space has 16-bit width)
CK
A21 to A0
CSn
D15 to D0
Internal
address bus
Internal
data bus
DMAC indirect
address buffer
DMAC data
buffer
RD
Transfer source
address (H)
Transfer source
address (L)
NOP
Indirect address
Transfer destina-
tion address
Indirect
address (H)
Transfer source
address^*1
Indirect
address (L)
NOP
Indirect
address
Transfer
data
Transfer
data
Indirect address
*2
Transfer data Transfer data
Indirect address
Transfer data
WRH, WRL
Address read cycle
(1st)
(2nd)
NOP
cycle
Data read cycle
(3rd)
Data write cycle
(4th)
Notes: 1. The internal address bus is controlled by the port and does not change.
2. The DMAC does not latch the value until 32-bit data is read from the internal data bus.
Figure 9.6 Dual Address Mode and Indirect Address Transfer Timing Example 1
161