SH7052 Datasheet, PDF (735/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

external memory, or in flash memory outside the address area, and execute the program from
there.
Notes: 1. Operation is not guaranteed if bits SWE1, ESU1, PSU1, EV1, PV1, E1, and P1 of
FLMCR1 are set/reset by a program in flash memory in the corresponding address
areas.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Programming should be performed in the erased state. Do not perform additional
programming on previously programmed addresses.
20.7.1 Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figures 20.13 and 20.14 should be followed. Performing program operations according to this
flowchart will enable data or programs to be written to flash memory without subjecting the
device to voltage stress or sacrificing program data reliability. Programming should be carried out
128 bytes at a time.
Following the elapse of 10 µs or more after the SWE1 bit is set to 1 in flash memory control
register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram
data area, and the 128-byte data in the program data area in RAM is written consecutively to the
program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128
consecutive byte data transfers are performed. The program address and program data are latched
in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128
bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of t_SPSU, the operating mode
is switched to program mode by setting the P1 bit in FLMCR1. The time during which the Pn bit
is set is the flash memory programming time. Follow the table in the programming flowchart for
the write time.
After the elapse of a given programming time, programming mode is exited. In exiting
programming mode, the P1 bit in FLMCR1 is cleared, then after an interval of t_CP or longer the
PSU1 bit is cleared, and after an interval of t_CPSU or longer the watchdog timer is halted.
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