SH7052 Datasheet, PDF (545/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 12—Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error
warning state caused by the receive error counter.
Bit 12: IRR4
0
1
Description
[Clearing condition]
Writing 1
Error warning state caused by receive error
[Setting condition]
When REC ≥ 96
(Initial value)
• Bit 11—Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error
warning state caused by the transmit error counter.
Bit 11: IRR3
0
1
Description
[Clearing condition]
Writing 1
Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
(Initial value)
• Bit 10—Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote
frame has been received in a mailbox (buffer).
Bit 10: IRR2
0
1
Description
[Clearing condition]
Clearing of all bits in RFPR (remote request wait register)
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed.
When corresponding MBIMR = 0.
(Initial value)
• Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer)
receive message has been received normally.
Bit 9: IRR1
0
1
Description
[Clearing condition]
Clearing of all bits in RXPR (receive complete register) when MBIMR is 0
(Initial value)
Data frame or remote frame received and stored in mailbox
[Setting conditions]
When data frame or remote frame reception is completed.
When corresponding MBIMR = 0.
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