SH7052 Datasheet, PDF (434/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

CR
Upper 8 bits
of POPCR
Compare-match
signal
GR11B
APC output pins
(PULS0 to PULS7)
Port function
selection
Reset signal
Set signal
Compare-match
signal
GRIIA
Lower 8 bits
of POPCR
Figure 11.2 Advanced Pulse Controller Output Operation
11.3.2 Advanced Pulse Controller Output Operation
Example of Setting Procedure for Advanced Pulse Controller Output Operation: Figure 11.3
shows an example of the setting procedure for advanced pulse controller output operation.
1. Set general registers GR11A and GR11B as output compare registers with the timer I/O
control register (TIOR).
2. Set the pulse rise point with GR11A and the pulse fall point with GR11B.
3. Select the timer counter 11 (TCNT11) counter clock with the timer prescale register (PSCR).
TCNT11 can only be cleared by an overflow.
4. Enable the respective interrupts with the timer interrupt enable register (TIER).
5. Set the pins for 1 output and 0 output with POPCR.
6. Set the control register for the port to be used by the APC to the APC output pin function.
7. Set the STR bit to 1 in the timer start register (TSTR) to start timer counter 11 (TCNT11).
8. Each time a compare-match interrupt is generated, update the GR value and set the next pulse
output time.
9. Each time a compare-match interrupt is generated, update the POPCR value and set the next
pin for pulse output.
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