SH7052 Datasheet, PDF (644/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.3.5 Port B Invert Register (PBIR)
Bit: 15
14
13
PB15IR PB14IR PB13IR
Initial value: 0
0
0
R/W: R/W R/W R/W
12
11
10
9
8
— PB11IR PB10IR PB9IR PB8IR
0
0
0
0
0
R
R/W R/W R/W R/W
Bit:
Initial value:
R/W:
7
PB7IR
0
R/W
6
PB6IR
0
R/W
5
PB5IR
0
R/W
4
PB4IR
0
R/W
3
PB3IR
0
R/W
2
PB2IR
0
R/W
1
PB1IR
0
R/W
0
PB0IR
0
R/W
The port B invert register (PBIR) is a 16-bit readable/writable register that sets the port B
inversion function. Bits PB15IR to PB13IR and PB11IR to PB0IR correspond to pins
PB15/PULS5/SCK2 to PB13/SCK0 and PB11/RxD4/HRxD0/TO8H to PB0/TO6A. PBIR is
enabled when port B pins function as ATU outputs or serial clock pins, and disabled otherwise.
When port B pins function as ATU outputs or serial clock pins, the value of a pin is inverted when
the corresponding bit in PBIR is set to 1.
PBIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
PBnIR
0
1
n = 15 to 0
Description
Value is not inverted
Value is inverted
(Initial value)
618