SH7052 Datasheet, PDF (194/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.4 Examples of Use
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, on-chip serial communication interface channel 0 (SCI0) receive data is
transferred to external memory using DMAC channel 0.
Table 9.5 indicates the transfer conditions and the set values of each of the registers.
Table 9.5 Transfer Conditions and Register Set Values for Transfer between On-chip SCI
and External Memory
Transfer Conditions
Transfer source: RDR0 of on-chip SCI0
Transfer destination: external memory
Transfer count: 64 times
Transfer source address: fixed
Transfer destination address: incremented
Transfer request source: SCI0 (RDR0)
Bus mode: cycle-steal
Transfer unit: byte
Interrupt request generation at end of transfer
DMAC master enable on
Register
SAR0
DAR0
DMATCR0
CHCR0
DMAOR
Value
H'FFFFF005
H'00400000
H'00000040
H'00020105
H'0001
9.4.2
Example of DMA Transfer between A/D Converter and On-Chip Memory
(Address Reload On)
In this example, on-chip A/D converter channel 0 is the transfer source and on-chip memory is the
transfer destination, and the address reload function is on.
Table 9.6 indicates the transfer conditions and the set values of each of the registers.
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