SH7052 Datasheet, PDF (562/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.3.2 Initialization after a Hardware Reset
After a hardware reset, the following initialization processing should be carried out:
1. IRR0 clearing
2. HCAN pin port settings
3. Bit rate setting
4. Mailbox transmit/receive settings
5. Mailbox (RAM) initialization
6. Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and
the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is
exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN
automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up
sequence then begins, and communication with the CAN bus is possible as soon as the sequence
ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.
IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby mode. As an HCAN interrupt is initiated immediately when interrupts are
enabled, IRR0 should be cleared.
HCAN Pin Port Settings: HCAN pin port settings must be made during or before bit
configuration. Refer to the section 18, Pin Function Controller (PFC), for details of the setting
method.
Bit Rate Settings: As bit rate settings, a baud rate setting and bit timing setting must be made
each time a CAN node begins communication. The baud rate and bit timing settings are made in
the bit configuration register (BCR).
Notes: 1. BCR can be written to at all times, but should only be modified in configuration mode.
2. Settings should be made so that all CAN controllers connected to the CAN bus have
the same baud rate and bit width.
3. Limits for the settable variables (TSEG1, TSEG2, BRP, sample point, and SJW) are
shown in table 15.4.
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