SH7052 Datasheet, PDF (789/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 21.8 Program/Program-Verify Parameter
Flow Section Item
Symbol Min Typ Max Unit Notes
Program/
Wait time after PSU1 bit t_SPSU
program-verify setting
50
50
—
µs
Wait time after P1 bit
t _SP10
8
10 12 µs Additional-
setting (10µs)
programming
time wait
Wait time after P1 bit
t _SP30
setting (30µs)
28 30 32 µs Programming
time wait
Wait time after P1 bit
setting (200µs)
t _SP200
198 200 202 µs
Programming
time wait
Wait time after P1 bit
t _CP
clearing
5
5
—
µs
Wait time after PSU1 bit t_CPSU
5
5
—
µs
clearing
Wait time after PV1 bit t_SPV
setting
4
4
—
µs
Wait time after dummy t_SPVR
2
2
—
µs
write
Wait time after PV1 bit t_CPV
clearing
2
2
—
µs
All
Wait time after SWE1 bit t_SSWE
1
1
—
µs
setting
Wait time after SWE1 bit t_CSWE
clearing
100 100 —
µs
21.7.3 Erase Mode
When erasing flash memory, the erase/erase-verify flowchart (single-block erase) shown in figure
21.15 should be followed for each block.
To perform data or program erasure, set the SWE1 bit to 1 in flash memory control register n
(FLMCR1), then, after an interval of t_SSWE or longer, make a 1-bit setting for the flash memory
area to be erased in erase block register 1 or 2 (EBR1, EBR2). Next, the watchdog timer is set to
prevent overerasing in the event of program runaway, etc. Set 19.8 ms as the WDT overflow
period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU1 bit in
FLMCR1, and after an interval of t_SESU or longer, the operating mode is switched to erase mode by
setting the E1 bit in FLMCR1. The time during which the E1 bit is set is the flash memory erase
time. Ensure that the erase time does not exceed t_SE.
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