SH7052 Datasheet, PDF (618/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

17.1.2 Block Diagram
Figure 17.1 shows a block diagram of the AUD.
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDRST
AUDMD
AUDCK
AUDSYNC
PC output circuit
Address buffer
Data buffer
Mode control
Bus
controller
Internal Peripheral
bus
module bus
On-chip
memory
CPU
On-chip
peripheral
module
Figure 17.1 AUD Block Diagram
17.2 Pin Configuration
Table 17.1 shows the AUD’s input/output pins.
Table 17.1 AUD Pins
Name
AUD data
AUD reset
AUD mode
AUD clock
AUD sync signal
Abbreviation
AUDATA3 to
AUDATA0
AUDRST
AUDMD
AUDCK
AUDSYNC
Function
Branch Trace Mode
RAM Monitor Mode
Branch destination address Monitor address/data
output
input/output
AUD reset input
AUD reset input
Mode select input (L)
Mode select input (H)
Serial clock (φ/2) output
Serial clock input
Data start position
identification signal output
Data start position
identification signal input
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