SH7052 Datasheet, PDF (457/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

13.2.2 Compare Match Timer Control/Status Register (CMCSR)
The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation. It is initialized to H'0000 by a power-on reset and in the standby
modes.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
CMF CMIE —
—
—
Initial value: 0
0
0
0
0
R/W: R/(W)* R/W
R
R
R
Note: * The only value that can be written is a 0 to clear the flag.
2
1
0
—
CKS1 CKS0
0
0
0
R
R/W R/W
• Bits 15 to 8 and 5 to 2—Reserved: These bits always read 0. The write value should always be
0.
• Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and
CMCOR values have matched.
Bit 7: CMF
0
1
Description
CMCNT and CMCOR values have not matched
[Clearing condition]
Write 0 to CMF after reading 1 from it
CMCNT and CMCOR values have matched
(Initial value)
• Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a
compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF =
1).
Bit 6: CMIE
0
1
Description
Compare match interrupt (CMI) disabled
Compare match interrupt (CMI) enabled
(Initial value)
431