SH7052 Datasheet, PDF (217/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 10.3 ATU-II Registers (cont)
Channel Name
Abbrevia-
Initial
tion
R/W Value Address
Access Size (Bits)
10
Correction counter
TCCLR10 R/W H'0000 H'FFFFF6E6 16
clear register 10
Timer status register TSR10
10
R/(W)* H'FFFF H'FFFFF6E8
Timer interrupt enable TIER10
register 10
R/W H'FFFF H'FFFFF6EA
11
Free-running counter TCNT11 R/W H'0000 H'FFFFF5C0 16
11
General register 11A GR11A R/W H'FFFF H'FFFFF5C2
General register 11B GR11B R/W H'FFFF H'FFFFF5C4
Timer I/O control
register 11
TIOR11 R/W H'00 H'FFFFF5C6 8
Timer control register TCR11
11
R/W H'00 H'FFFFF5C8
Timer status register TSR11
11
R/(W)* H'0000 H'FFFFF5CA 16
Timer interrupt enable TIER11
register 11
R/W H'0000 H'FFFFF5CC
Note: * 0 write after a read
191