SH7052 Datasheet, PDF (168/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 9.1 DMAC Registers (cont)
Channel Name
Abbr.
Initial
R/W Value
Address
Register Access
Size
Size
3
DMA source
SAR3
R/W Undefined H'FFFFECF0 32 bits 16, 32*²
address register 3
DMA destination DAR3
address register 3
R/W Undefined H'FFFFECF4 32 bits 16, 32*²
DMA transfer
count register 3
DMATCR3 R/W Undefined H'FFFFECF8 32 bits 16, 32*³
DMA channel
control register 3
CHCR3
R/W*¹ H'00000000 H'FFFFECFC 32 bits
16, 32*²
Shared DMA operation
register
DMAOR R/W*¹ H'0000
H'FFFFECB0 16 bits 16*⁴
Notes: Word access to a register takes 3 cycles, and longword access 6 cycles.
1. Write 0 after reading 1 in bit 1 of CHCR0 to CHCR3 and in bits 1 and 2 of DMAOR to
clear flags. No other writes are allowed.
2. For 16-bit access of SAR0 to SAR3, DAR0 to DAR3, and CHCR0 to CHCR3, the 16-bit
value on the side not accessed is held.
3. DMATCR has a 24-bit configuration: bits 0 to 23. Writing to the upper 8 bits (bits 24 to
31) is invalid, and these bits always read 0.
4. Do not use 32-bit access on DMAOR.
5. Do not attempt to access an empty address, as operation canot be guaranteed if this is
done.
9.2 Register Descriptions
9.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3)
DMA source address registers 0 to 3 (SAR0 to SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a count function, and during a
DMA transfer, they indicate the next source address.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The initial value after a power-on reset and in standby mode is undefined.
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