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SH7052 Datasheet, PDF (463/919 Pages) Renesas Technology Corp – SuperHTM RISC engine
13.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 13.7 shows the timing.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT
Internal
write signal
CMCNT input
clock
CMCNT
N
M
CMCNT write data
Figure 13.7 CMCNT Word Write and Increment Contention
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