SH7052 Datasheet, PDF (553/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit x: LAFMHx
0
1
Description
Stored in MC0 and MD0 (receive-only mailbox) depending on bit match
between MC0 message identifier and receive message identifier
(Initial value)
Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match
between MC0 message identifier and receive message identifier
• LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be
0.
• LAFMH Bits 9 and 8, LAFML bits 15 to 0—18-Bit Identifier Filter (LAFMH1, 0, LAFML15
to 0): Filter mask bits for the 18 bits of the receive message identifier (extended).
Bit x: LAFMHx
LAFMLx
0
1
Description
Stored in MC0 and MD0 (receive-only mailbox) depending on bit match
between MC0 message identifier and receive message identifier
(Initial value)
Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match
between MC0 message identifier and receive message identifier
15.2.18 Message Control (MC0 to MC15)
The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers
(MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15).
The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).
MCx [1]
Bit: 7
6
5
4
3
2
1
0
DLC3 DLC2 DLC1 DLC0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
MCx [2]
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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