SH7052 Datasheet, PDF (532/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.2 Register Descriptions
15.2.1 Master Control Register (MCR)
The master control register (MCR) is an 8-bit readable/writable register that controls the CAN
interface.
Bit: 7
6
5
4
MCR7 — MCR5 —
Initial value: 0
0
0
0
R/W: R/W
—
R/W
—
3
2
1
0
— MCR2 MCR1 MCR0
0
0
0
1
—
R/W R/W R/W
• Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release
by bus operation.
Bit 7: MCR7
0
1
Description
HCAN sleep mode release by CAN bus operation disabled
HCAN sleep mode release by CAN bus operation enabled
(Initial value)
• Bit 6—Reserved: This bit always reads 0. The write value should always be 0.
• Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition.
Bit 5: MCR5
0
1
Description
HCAN sleep mode released
Transition to HCAN sleep mode enabled
(Initial value)
• Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0.
• Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit
messages.
Bit 2: MCR2
0
1
Description
Transmission order determined by message identifier priority (Initial value)
Transmission order determined by mailbox (buffer) number priority
(TXPR1 > TXPR15)
506