SH7052 Datasheet, PDF (857/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

24.3.5 Advanced Timer Unit Timing and Advance Pulse Controller Timing
Table 24.10 shows advanced timer unit timing and advanced pulse controller timing.
Table 24.10 Advanced Timer Unit Timing and Advanced Pulse Controller Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 85°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing flash EEPROM, T_a = –40°C to 85°C.
Item
Output compare output delay time
Input capture input setup time
PULS output delay time
Timer clock input setup time
Timer clock pulse width (single edge
specified)
Timer clock pulse width (both edges
specified)
Symbol
t _TOCD
t _TICS
t _PLSD
t _TCKS
t _TCKWH/L
t _TCKWH/L
Min
—
24*¹
24 + t_cyc
—
24*¹
24 + t_cyc
3.0
Max
100
—
100
—
—
5.0
—
Unit Figures
ns
Figure 24.11
ns
ns
ns
Figure 24.12
t _cyc
t _cyc
[Operating precautions]
*1 The timer input signals and timer clock input signals are asynchronous, but judged to have
been changed at clock rise with two-state intervals shown in figures 24.11 and 24.12. If the
setup times shown here are not provided, recognition is delayed until the clock rise two states
after that timing.
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