SH7052 Datasheet, PDF (568/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt
source settings and data settings must be made. Interrupt source settings are made in the mailbox
interrupt mask register (MBIMR) and interrupt mask register (IMR), while transmit data settings
are made by writing the following three kinds of necessary data in the message control registers
(MCx[1] to MCx[8]) and message data registers (MDx[1] to MDx[8]).
1. CPU interrupt source settings
Transmission acknowledge and transmission abort acknowledge interrupts can be masked for
individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR)
interrupts can be masked in the interrupt mask register (IMR).
2. Arbitration field
In the arbitration field, the 11-bit identifier (STD_ID0 to STD_ID10) and RTR bit (standard
format) or 29-bit identifier (STD_ID0 to STD_ID10, EXT_ID0 to EXT_ID17) and IDE.RTR
bit (extended format) are set. The registers to be set are MCx[5] to MCx[8].
3. Control field
In the control field, the byte length of the data to be transmitted is set in DLC0 to DLC3. The
register to be set is MCx[1].
4. Data field
In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The
registers to be set are MDx[1] to MDx[8].
The number of bytes in the data actually transmitted depends on the data length code (DLC) in the
control field. If a value exceeding the value set in DLC is set in the data field, only the number of
bytes set in DLC will actually be transmitted.
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