SH7052 Datasheet, PDF (29/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 1.1 SH7052F/SH7053F/SH7054F Features (cont)
Item
Clock pulse
generator
(CPG/PLL)
Interrupt
controller (INTC)
User break
controller (UBC)
Bus state
controller (BSC)
Features
• On-chip clock pulse generator (maximum operating frequency: 40 MHz)
• Independent generation of CPU system clock and peripheral clock for
peripheral modules
• On-chip clock-multiplication PLL circuit (×4)
Internal clock frequency range: 5 to 10 MHz
• Five external interrupt pins (NMI, IRQ0 to IRQ3)
• 109 internal interrupt sources
(ATU-II × 75, SCI × 20, DMAC × 4, A/D × 2, WDT × 1, UBC × 1, CMT × 2,
HCAN × 4)
• 16 programmable priority levels
• Requests an interrupt when the CPU or DMAC generates a bus cycle with
specified conditions (interrupt can also be masked)
• Trigger pulse output (UBCTRG) on break condition
 Selection of trigger pulse width (φ ×1, ×4, ×8, ×16)
• Simplifies configuration of an on-chip debugger
• Supports external memory access (SRAM and ROM directly connectable)
 8/16-bit bus space
• 3.3 V bus interface
• 16 MB address space divided into four areas, with the following parameters
settable for each area:
 Bus size (8 or 16 bits)
 Number of wait cycles
 Chip select signals (CS0 to CS3) output for each area
• Wait cycles can be inserted using an external WAIT signal
• External access in minimum of two cycles
• Provision for idle cycle insertion to prevent bus collisions
3