SH7052 Datasheet, PDF (535/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bits 15 and 14—Re-synchronization Jump Width (SJW): These bits set the maximum bit
synchronization range.
Bit 15:
BCR7
0
1
Bit 14:
BCR6
0
1
0
1
Description
Maximum bit synchronization width = 1 time quantum
Maximum bit synchronization width = 2 time quanta
Maximum bit synchronization width = 3 time quanta
Maximum bit synchronization width = 4 time quanta
• Bits 13 to 8—Baud Rate Prescale (BRP): These bits are used to set the CAN bus baud rate.
Bit 13:
BCR5
0
0
0
⋅
⋅
⋅
1
Bit 12:
BCR4
0
0
0
⋅
⋅
⋅
1
Bit 11:
BCR3
0
0
0
⋅
⋅
⋅
1
Bit 10:
BCR2
0
0
0
⋅
⋅
⋅
1
Bit 9:
BCR1
0
0
1
⋅
⋅
⋅
1
Bit 8:
BCR0
0
1
0
⋅
⋅
⋅
1
Description
2 × system clock
4 × system clock
6 × system clock
⋅
⋅
⋅
128 × system clock
(Initial value)
1-bit time
1-bit time (8–25 time quanta)
SYNC_SEG
1
PRSEG
PHSEG1
TSEG1 (time segment 1)*
2–16
PHSEG2
TSEG2 (time segment 2)*
2–8
Quantum
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal
bit edge transitions occur in this segment.)
PRSEG: Segment for compensating for physical delay between networks.
PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronization (re-synchronization) is established.)
PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is
shortened when synchronization (re-synchronization) is established.)
Note: * The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
Figure 15.2 Detailed Description of One Bit
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