|
SH7052 Datasheet, PDF (244/919 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
|
◁ |
Timer Control Register 11 (TCR11)
Bit: 7
â
Initial value:
0
R/W: R
6
5
4
â
CKEG1 CKEG0
0
0
0
R
R/W
R/W
3
2
1
0
â CKSELA2 CKSELA1 CKSELA0
0
0
0
0
R
R/W
R/W
R/W
⢠Bits 7, 6, and 3âReserved: These bits always read 0. The write value should always be 0.
⢠Bits 5 and 4âEdge Select: These bits select the event counter counted edge(s).
Bit 5: CKEG1
0
1
Bit 4: CKEG0
0
1
0
1
Description
Rising edges counted
Falling edges counted
Both rising and falling edges counted
Count disabled
(Initial value)
⢠Bits 2 to 0âClock Select A2 to A0 (CKSELA2 to CKSELA0): These bits select clock Ï",
scaled from the internal clock source, from Ï', Ï'/2, Ï'/4, Ï'/8, Ï'/16, and Ï'/32.
Bit 2:
CKSELA2
0
1
Bit 1:
CKSELA1
0
1
0
1
Bit 0:
CKSELA0
0
1
0
1
0
1
0
1
Description
Internal clock Ï": counting on Ï'
(Initial value)
Internal clock Ï": counting on Ï'/2
Internal clock Ï": counting on Ï'/4
Internal clock Ï": counting on Ï'/8
Internal clock Ï": counting on Ï'/16
Internal clock Ï": counting on Ï'/32
External clock: counting on TCLKA pin input
External clock: counting on TCLKB pin input
218
|
▷ |