SH7052 Datasheet, PDF (755/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

A18 to A0
CE
OE
Address stable
t_ce
t_oe
Address stable
t_ce
t_oe
WE _VIH
t_acc
I/O7 to I/O0
t_acc
t_oh
t_df
t_oh ^tdf
Figure 20.24 CE and OE Clock System Read Timing Waveforms
20.11.4 Auto-Program Mode
1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
3. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
4. Memory address transfer is performed in the second cycle (figure 20.25). Do not perform
transfer after the second cycle.
5. Do not perform a command write during a programming operation.
6. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
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