SH7052 Datasheet, PDF (239/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Timer Control Registers 6A, 6B, 7A, 7B (TCR6A, TCR6B, TCR7A, TCR7B)
TCR6A, TCR7A
Bit: 7
6
5
4
3
2
1
0
— CKSELB2 CKSELB1 CKSELB0 — CKSELA2 CKSELA1 CKSELA0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
TCR6B, TCR7B
Bit: 7
6
5
4
3
2
1
0
— CKSELD2 CKSELD1 CKSELD0 — CKSELC2 CKSELC1 CKSELC0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R/W
R/W
R/W
R
R/W
R/W
R/W
• Bit 7—Reserved: This bit always reads 0. The write value should always be 0.
• Bits 6 to 4—Clock Select B2 to B0, D2 to D0 (CKSELB2 to CKSELB0, CKSELD2 to
CKSELD0): These bits select clock φ", scaled from the internal clock source, from φ', φ'/2,
φ'/4, φ'/8, φ'/16, and φ'/32.
Bit 6:
CKSELx2
0
1
x = B or D
Bit 5:
CKSELx1
0
1
0
1
Bit 4:
CKSELx0
0
1
0
1
0
1
0
1
Description
Internal clock φ": counting on φ'
Internal clock φ": counting on φ'/2
Internal clock φ": counting on φ'/4
Internal clock φ": counting on φ'/8
Internal clock φ": counting on φ'/16
Internal clock φ": counting on φ'/32
Setting prohibited
Setting prohibited
(Initial value)
• Bit 3—Reserved: This bit always reads 0. The write value should always be 0.
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