SH7052 Datasheet, PDF(201/919 Page) Renesas Technology Corp – SuperHTM RISC engine

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SH7052 Datasheet, PDF (201/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

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â¢ Channel 10 has a 32-bit output compare and input capture register, free-running counter, 16-bit

free-running counter, output compare/input capture register, reload register, 8-bit event

counter, and output compare register, and four 16-bit reload counters, allowing the following

operations:

ï£§ Capture on external input pin edge input

ï£§ Reload count possible with 32, 64, 128, or 256 times the captured value

ï£§ Internal clock generated by reload counter underflow can be used as 16-bit free-running

counter input

ï£§ Channel 1 and 2 free-running counter clearing capability

â¢ Channel 11 has one 16-bit free-running counter and two 16-bit general registers, allowing the

following operations:

ï£§ Two general registers can be used for compare-match

ï£§ Compare-match signal can be output to APC

â¢ High-speed access to internal 16-bit bus

ï£§ High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and

capture registers

â¢ 75 interrupt sources

ï£§ Four input capture interrupt requests, one overflow interrupt request, and one interval

interrupt request for channel 0

ï£§ Sixteen dual input capture/compare-match interrupt requests and two counter overflow

interrupt requests for channels 1 and 2

ï£§ Twelve dual input capture/compare-match interrupt requests and three overflow interrupt

requests for channels 3 to 5

ï£§ Eight compare-match interrupts for channels 6 and 7

ï£§ Sixteen one-shot end interrupt requests for channel 8

ï£§ Six compare-match interrupts for channel 9

ï£§ Two compare-match interrupts and one dual-function input capture/compare-match

interrupt for channel 10

ï£§ Two dual input capture/compare-match interrupt requests and one overflow interrupt

request for channel 11

â¢ Direct memory access controller (DMAC) activation

ï£§ The DMAC can be activated by a channel 0 input capture interrupt (ICI0A to D)

ï£§ The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt

(CMI6A to D)

ï£§ The DMAC can be activated by a channel 7 cycle register 7 compare-match interrupt

(CMI7A to D)

â¢ A/D converter activation

ï£§ The A/D converter can be activated by detection of 1 in bits ITVA6 to 13 of the channel 0

interval interrupt request registers (ITVRR1, ITVRR2A, ITVRR2B)

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