SH7052 Datasheet, PDF (551/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.2.15 Transmit Error Counter (TEC)
The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter
indicating the number of transmit message errors on the CAN bus. The count value is stipulated in
the CAN protocol.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
15.2.16 Unread Message Status Register (UMSR)
The unread message status register (UMSR) is a 16-bit readable/writable register containing status
flags that indicate, for individual mailboxes (buffers), that a received message has been
overwritten by a new receive message before being read. When an unread message is overwritten
by a new receive message, the old data is lost.
Bit:
Initial value:
R/W:
15
UMSR7
0
R/W
14
UMSR6
0
R/W
13
UMSR5
0
R/W
12
UMSR4
0
R/W
11
UMSR3
0
R/W
10
UMSR2
0
R/W
9
UMSR1
0
R/W
8
UMSR0
0
R/W
Bit: 7
6
5
4
3
2
1
0
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 to 0—Unread Message Status Flags (UMSR7 to 0, UMSR15 to 8): Status flags
indicating that an unread receive message has been overwritten.
Bit x: UMSRx
0
1
Description
[Clearing condition]
Writing 1
Unread receive message is overwritten by a new message
[Setting condition]
When a new message is received before RXPR is cleared
(Initial value)
525