SH7052 Datasheet, PDF (795/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Error protection is released only by a power-on reset and in hardware standby mode.
Figure 21.16 shows the flash memory state transition diagram.
Program mode
Erase mode
RES = 0 or HSTBY = 0
Reset or standby
(hardware protection)
RD VF PR ER FLER = 0
RD VF PR ER FLER = 0
Error
occurrence
Error occurrence
(software standby)
RES = 0 or
HSTBY = 0
RES = 0 or
HSTBY = 0
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Error protection mode
Software
standby mode
Error protection mode
(software standby)
RD VF PR ER FLER = 1
Software standby
mode release
RD VF PR ER FLER = 1
FLMCR1, FLMCR2, EBR1,
EBR2 initialization state
Legend
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 21.16 Flash Memory State Transitions
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