SH7052 Datasheet, PDF (776/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit. (Do not set more than one bit, as this will automatically clear both EBR1
and EBR2 to 0.) When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory block configuration is shown in table 21.5.
Bit: 7

Initial value: 0
R/W: R
6
5
4
3
2
1
0

EB13 EB12 EB11 EB10 EB9 EB8
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Table 21.4 Flash Memory Erase Blocks
Block (Size)
EB0 (4 kB)
EB1 (4 kB)
EB2 (4 kB)
EB3 (4 kB)
EB4 (4 kB)
EB5 (4 kB)
EB6 (4 kB)
EB7 (4 kB)
EB8 (32 kB)
EB9 (64 kB)
EB10 (64 kB)
EB11 (64 kB)
EB12 (64 kB)
EB13 (64 kB)
Addresses
H'000000 to H'000FFF
H'001000 to H'001FFF
H'002000 to H'002FFF
H'003000 to H'003FFF
H'004000 to H'004FFF
H'005000 to H'005FFF
H'006000 to H'006FFF
H'007000 to H'007FFF
H'008000 to H'00FFFF
H'010000 to H'01FFFF
H'020000 to H'02FFFF
H'030000 to H'03FFFF
H'040000 to H'04FFFF
H'050000 to H'05FFFF
750