SH7052 Datasheet, PDF (305/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 0—One-Shot Pulse Interrupt Enable 8A (OSE8A): Enables or disables interrupt requests
by OSF8A in TSR8 when OSF8A is set to 1.
Bit 0: OSE8A
0
1
Description
OSI8A interrupt requested by OSF8A is disabled
OSI8A interrupt requested by OSF8A is enabled
(Initial value)
Timer Interrupt Enable Register 9 (TIER9)
TIER9 controls enabling/disabling of channel 9 event counter compare-match interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
— CME9F CME9E CME9D CME9C CME9B CME9A
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
• Bits 15 to 6—Reserved: These bits always read 0. The write value should always be 0.
• Bit 5—Compare-Match Interrupt Enable 9F (CME9F): Enables or disables interrupt requests
by CMF9F in TSR9 when CMF9F is set to 1.
Bit 5: CME9F
0
1
Description
CMI9F interrupt requested by CMF9F is disabled
CMI9F interrupt requested by CMF9F is enabled
(Initial value)
• Bit 4—Compare-Match Interrupt Enable 9E (CME9E): Enables or disables interrupt requests
by CMF9E in TSR9 when CMF9E is set to 1.
Bit 4: CME9E
0
1
Description
CMI9E interrupt requested by CMF9E is disabled
CMI9E interrupt requested by CMF9E is enabled
(Initial value)
279