SH7052 Datasheet, PDF (609/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.4.3 Analog Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D
converter samples the analog input at time t_D (A/D conversion start delay time) after the ADST bit
is set to 1, then starts conversion. Figure 16.6 shows the A/D conversion timing.
The A/D conversion time (t_CONV) includes t_D and the analog input sampling time (t_SPL). The length
of t_D is not fixed, since it includes the time required for synchronization of the A/D conversion
operation. The total conversion time therefore varies within the ranges shown in table 16.4.
In scan mode, the t_CONV values given in table 16.4 apply to the first conversion. In the second and
subsequent conversions, t_CONV is fixed at 512 states when CKS = 0 or 256 states when CKS = 1.
Table 16.4 A/D Conversion Time (Single Mode)
Item
A/D conversion start
delay time
Input sampling time
A/D conversion time
Symbol Min
t_D
20
CKS = 0
Typ Max
— 34
t _SPL
t _CONV
— 128 —
518 — 532
CKS = 1
Min Typ Max
12 — 18
— 64 —
262 — 268
Unit
States
(φ base)
583