SH7052 Datasheet, PDF (581/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.3.7 Interrupt Interface
There are 12 interrupt sources for each HCAN channel. Four independent interrupt vectors are
assigned to each channel. Table 15.5 lists the HCAN interrupt sources.
With the exception of the power-on reset processing vector (IRR0), these sources can be masked.
Masking is implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask
register (IMR).
Table 15.5 HCAN Interrupt Sources
Channel IPR Bits
HCAN
IPRL
(11 to 8)
(initial
value)
Vector
Vector Number IRR Bit
ERS 220
IRR5
IRR6
OVR 221
IRR0
IRR2
IRR3
IRR4
IRR7
RM0 222
SLE0 223
IRR9
IRR12
IRR1
IRR1
IRR8
Description
Error passive interrupt (TEC ≥ 128 or REC ≥
128)
Bus off interrupt (TEC ≥ 256)
Power-on reset processing interrupt
Remote frame reception interrupt
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Overload frame transmission interrupt/bus off
recovery interrupt (11 recessive bits × 128
times)
Unread message overwrite interrupt
HCAN sleep mode CAN bus operation
interrupt
Mailbox 0 message reception interrupt
Mailbox 1 to 15 message reception interrupt
Message transmission/cancellation interrupt
555