SH7052 Datasheet, PDF (725/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the
error-protection state.
Bit 7: FLER
0
1
Description
Flash memory is operating normally
(Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Power-on reset or hardware standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See 20.8.3 Error Protection
• Bits 6 to 0—Reserved: These bits always read 0. The write value should always be 0.
20.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the
SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be
erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can
be set. Do not set more than one bit. (Do not set more than one bit, as this will automatically clear
both EBR1 and EBR2 to 0.) When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
The flash memory block configuration is shown in table 20.4.
Bit: 7
6
5
4
3
2
1
0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
20.5.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin. Bits 3 to 0 will be initialized to 0 if bit SWE1 is not set,
even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding
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