SH7052 Datasheet, PDF (569/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Message Transmission and Interrupts:
1. Message transmission wait
If message transmission is to be performed after completion of the message control (MCx[1] to
MCx[8]) and message data (MDx[1] to MDx[8]) settings, transmission is started by setting the
corresponding mailbox transmit wait bit (TXPR1 to TXPR15) to 1 in the transmit wait register
(TXPR). The following two transmission methods can be used:
a. Transmission order determined by mailbox number priority
b. Transmission order determined by message identifier priority
When the message identifier priority method is selected, if a number of messages are
designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer
in low-to-high mailbox order (priority order: mailbox 1 > mailbox 15). CAN bus arbitration is
then carried out for the messages in the transmit buffer, and message transmission is performed
when the bus is acquired.
When the mailbox number priority method is selected, if a number of messages are designated
as waiting for transmission (TXPR = 1), the message with the highest priority set in the
message identifier (MCx[5] to MCx[8]) is stored in the transmit buffer. CAN bus arbitration is
then carried out for the message in the transmit buffer, and message transmission is performed
when the transmission right is acquired. When the TXPR bit is set, internal arbitration is
performed again, the highest-priority message is found and stored in the transmit buffer, CAN
bus arbitration is carried out in the same way, and message transmission is performed when the
transmission right is acquired.
2. Message transmission completion and interrupt
When a message is transmitted error-free using the above procedure, The corresponding
acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) and
transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) are automatically
initialized. If the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask
register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register
(IMR) are set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
3. Message transmission cancellation
Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait
message. A transmit wait message is canceled by setting the bit for the corresponding mailbox
(TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is
executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is
set to 1 in the abort acknowledge register (ABACK). An interrupt can be requested. If the
corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR)
and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are set to the
interrupt enable value at this time, an interrupt can be sent to the CPU.
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